1. Field of the Invention
This invention relates to a semiconductor memory device. More specifically, this invention relates to an on-chip scramble circuit for memory test (property evaluation), in the case where a defective cell in a regular cell array is replaced by a redundancy cell in a semiconductor memory device adopting a bit line twist system.
2. Description of the Related Art
As is well known, there has been proposed a semiconductor memory device adopting a bit line twist system, in which at least a part of a plurality of bit lines are twisted (for example, refer to Jpn. Pat. Appln. KOKAI Pub. No. 62-51096). Adopting the bit line twist system in a semiconductor memory device is very effective in reducing coupling noise from adjacent bit lines in operation of the bit line when data is read out from and written in a memory cell.
A problem of a semiconductor memory device caused by adopting the bit line twist system is consistency of redundancy cell data. Specifically, if the bit line twist system is adopted, the data direction (phase) of a redundancy cell connected to a word line in which a redundancy replacement has been performed changes according to the address of the word line for which redundancy is performed. This is because each redundancy cell is connected with one of complementary bit lines. Therefore, depending on the address of the word line, there are cases where the data direction of a redundancy cell which has performed redundancy replacement is reverse to the data direction of the regular cell (defective cell) which has been replaced. As described above, unless the address of the word line in which redundancy replacement is performed is restricted, the data direction of the redundancy cell cannot be conformed to the data direction of the defective cell.
As described above, as a measure against noise due to interference between adjacent bit lines, various bit line twist systems have been proposed. However, in a conventional semiconductor memory device adopting a bit line twist system, unless the address of the word line in which redundancy replacement is performed is restricted, it is difficult to conform the data direction of the redundancy cell which has performed redundancy replacement to the data direction of the defective cell which has been replaced. Therefore, in a memory test after a redundancy replacement, there is a problem that the redundancy cell which has replaced cannot be properly evaluated.